1. Field of the Invention
The present invention relates to a semiconductor memory device and methods of manufacturing and operating the same. More particularly, the present invention relates to a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and methods of manufacturing and operating the same.
2. Description of the Related Art
A unit cell of a semiconductor memory device, such as a dynamic random access memory (DRAM), includes a single transistor and a single capacitor. In order to increase a packing density of a semiconductor memory cell, a volume of a transistor and/or a capacitor should be reduced. In the early stages of semiconductor memory devices, photolithography provided a sufficient margin that allowed the packing density of semiconductor memory devices to be increased just by decreasing the volumes of respective elements. Presently, however, if the packing density of semiconductor memory devices is to be further increased, a new method is required.
The packing density of semiconductor memory devices is also closely related to design rules. Accordingly, design rules may be narrowed in order to increase the packing density of the semiconductor memory devices. In this case, photolithography and etching process margins may be significantly lowered. Here, lowered process margins mean that a photolithography process should be performed more precisely. If a photolithography process margin is lowered, yield may be excessively decreased. Therefore, a new method capable of increasing the packing density of semiconductor devices and increasing the yield is required.
To meet this demand, semiconductor memory devices having quite atypical structures, in which a data storage medium, e.g., giant magnetoresistance (GMR) or tunneling magnetoresistance (TMR) having a data storage operation different from that of a well-known capacitor, is provided over the upper side of a transistor, have been introduced.
Recently, a SONOS memory device has been introduced as a semiconductor memory device in an attempt to meet these requirements. FIG. 1 illustrates a cross-sectional view of a conventional SONOS memory device (hereinafter referred to as a conventional memory device).
Referring to FIG. 1, a source region 12 and a drain region 14 are formed by implanting n-type impurities into a p-type semiconductor substrate 10 (hereinafter referred to as a semiconductor substrate). A channel region 16 is defined between the source and drain regions 12 and 14. A gate stack structure 18 is formed on the channel region 16 of the semiconductor substrate 10. The gate stack structure 18 is formed of a tunneling oxide layer 18a, a silicon nitride (Si3N4) layer 18b, a barrier oxide layer 18c, and a gate electrode 18d. The tunneling oxide layer 18a contacts the source and drain regions 12 and 14. The silicon nitride layer 18b has a trap site of a predetermined density. Accordingly, when the gate electrode 18d is supplied with a predetermined voltage, electrons pass through the tunneling oxide layer 18a and are trapped in the trap site of the silicon nitride layer 18b. The barrier oxide layer 18c blocks migration of the electrons toward the gate electrode 18d during the charge trapping.
In the conventional memory device, a threshold voltage varies according to whether electrons are trapped at the trap site of the silicon nitride layer 18b. Using this characteristic, information can be stored in and read out from the conventional memory device.
Because the electron trap site is within the silicon nitride layer in the conventional memory device, sufficient electrons to control a threshold voltage of a channel can be stored. However, only one bit of information can be stored in a single unit cell.
Thus, in the case of the conventional memory device, the volume of the memory device has to be decreased in order to increase the packing density. However, as design rules narrow, there is a limit to increasing the packing density merely by decreasing the volume of the memory device.